The present invention relates generally to a thin film transistor array and a method for fabricating the same. More particularly, the present invention relates to a thin film transistor array which is used, for example, in a liquid crystal display and the like and which is free from electrostatic damage during a manufacturing process thereof, and to a method for manufacturing such thin film transistor array.
In the field of a thin film transistor array used, for example, in a liquid crystal display and the like, one of the most important problems to be solved is to decrease or avoid electrostatic damage, such as damage of conductors or insulating films and occurrence of abnormal characteristics of the thin film transistor (TFT), caused by electrification during a fabrication process of the TFT array or by abnormal discharge in a film forming apparatus and the like.
Conventionally, in order to avoid such disadvantage, all the gate wiring and signal lines coupled to the thin film transistor array are coupled to a common line via a resistor having low resistance. Thereby, potential of all the gate wirings and the signal lines is equalized, so that occurrence of the electrostatic damage can be decreased.
However, in this method, since all the gate wirings and signal lines have the same potential, it was impossible to perform an inspection for detecting defects of TFTs and the like after finishing a fabricating process thereof.
That is, in the inspection for detecting defects of the TFTs and the like, a predetermined potential voltage is applied sequentially to the gate wirings and the signal lines and each TFT for display is turned on, thereby an electric charge is stored in each of pixel electrodes of a liquid crystal display device. Then, a predetermined potential voltage is again sequentially applied to the gate wirings and the signal lines and each of the TFTs for display is turned off, so that electric charge stored in each of the pixel electrodes is hold for a predetermined time period. Thereafter, a predetermined potential voltage is again applied and each of the TFTs for display is turned on, thereby electric charge stored in each pixel electrode is leaked to the corresponding signal line. By measuring the quantity of the leaked electric charge, defect of the TFT for display, break or short circuit of wiring, and the like are detected.
However, in the above-mentioned conventional technique, since all the gate wirings and the signal lines are connected to a common line via a resistor having low resistance, current leakage occurs between the gate wirings and between the signal lines when, in the inspection for detecting defects, a predetermined voltage of several volts through several ten volts is sequentially applied to the gate wirings and the signal lines. Therefore, it was impossible to perform the inspection for detecting defects in the TFTs for display with high precision. To this end, a device having a thin film transistor array including one or more defective TFTs is sometimes passed to the next manufacturing process, and it was impossible to sufficiently reduce defective device.
In order to improve such disadvantage, Japanese patent laid-open publication No. 3-296725 and so on disclose a technique of forming nonlinear elements each comprising a pair of TFTs between a gate wiring and a common line on the gate wiring side and between a signal line and a common line on the signal line side.
In such prior art technique, the nonlinear elements are formed respectively between each of the gate wirings and the common line on the gate wiring side and between each of the signal lines and the common line on the signal line side. Therefore, in a manufacturing process after a process of forming TFTs, when a high potential voltage is applied to a particular gate wiring or signal line due to electrification and the like, the resistance of the nonlinear element connected to the gate wiring or the signal line becomes a relatively small value. Thus, it is possible to make a current caused by the high potential voltage escape into the common line on the gate wiring side or into the common line on the signal line side via the nonlinear elements. Also, when a relatively low voltage from several volts through several ten volts is applied to the gate wirings or the signal lines in the inspection for detecting defects of the TFTs for display, performed after finishing the TFT forming process, the nonlinear elements reveal a relatively large resistance of 1 giga-ohm or more. Therefore, current leak does not occur between the gate wirings or between the signal lines, and it is possible to perform the inspection for detecting defects of the TFTs for display in relatively high precision. Thus, taking the detected result of the inspection into consideration, it is possible to fix defects and to prevent defective thin film transistor arrays from passing into the next fabrication process.
During the fabricating process of the TFTs, however, there is a possibility of occurrence of a rush current and the like between the common line on the gate wiring side and the gate wiring, due to static electricity and the like. In such case, even when the above-mentioned technique is used, disadvantages occur, such as destruction of the gate wiring in which the rush current occurred, short circuit between the gate wiring and the common line due to the melting of the conductor film forming the gate wiring or the common line, or destruction of insulating film or occurrence of abnormal characteristic in the TFT for display connected to the wiring in which rush current flowed. These disadvantages can be detected in the inspection for detecting defects after finishing the fabrication process of the TFTs, but can cause some deterioration of production yield.
Explanation will be made on these disadvantages with reference to the drawings. FIG. 16 is a plan view showing a structure around a TFT for display 18 and around a nonlinear element 51 formed between a gate wiring 13 and a common line on the gate wiring side 56 of a conventional thin film transistor array. FIG. 17 is a cross sectional view taken along the line E-E of FIG. 16. FIG. 18 is a circuit diagram showing an equivalent circuit of the nonlinear element 51 shown in FIG. 16. FIG. 19 is a plan view showing a structure during a process of forming the TFT array shown in FIG. 16, after the completion of a semiconductor film.
As shown in FIGS. 16, 17 and 19, the common line on the gate wiring side 56 and the gate wiring 13 are close to each other at an area between a gate electrode portion 50 and a gate electrode portion 49 of a nonlinear element 51 which portions are integrally formed with the common line on the gate wiring side 56 and the gate wiring 13, respectively. The distance between the gate electrode portions 50 and 49 are approximately several micrometers (microns) through several tens micrometers. Therefore, during a halfway process before finishing a fabrication process of TFTs, when a high potential voltage is applied to a particular gate wiring 13, due to electrification or abnormal discharge and the like, and a voltage difference between the common line on the gate wiring side 56 and the gate wiring 13 becomes large, there often occurs a condition in which the voltage difference exceeds the withstand voltage between the common line 56 and the gate wiring 13. Therefore, a rush current flows between the gate electrodes 49 and 50 of the nonlinear element 51.
Especially, the above-mentioned disadvantages such as the electrification, the abnormal discharge and the like often occur in a process in which a device to be fabricated is exposed to a plasma for a relatively long time, for example, in a film forming process using CVD method, a dry etching process, and the like. Therefore, in the conventional thin film transistor array, it was difficult to decrease an electrostatic damage, such as damage of wirings or insulating films, which occurs in a halfway process before the completion of a TFT fabricating process, for example, in a process of forming a film such as a gate insulating film or a semiconductor film or in the dry etching process.
Also, the common line on the gate wiring side 56 is formed outside a region where the TFTs for display are disposed, that is, on the edge portion of an insulating substrate. Therefore, the common line on the gate wiring side 56 tends to receive electrostatic voltage by the contact with various apparatuses and the like used in the fabrication process of the TFT and to receive electrical discharge from such apparatuses.
Further, since the common line on the gate wiring side 56 and the gate wiring 13 extend in a relation at right angles to each other, the common line on the gate wiring side 56 is close to all the several hundred through more than a thousand of the gate wirings 13. When the potential difference between a particular gate wiring and the common line on the gate wiring side 56 exceeds the withstand voltage therebetween due to electrification, abnormal discharge and the like and thereby the rush current occurrs, potential of the common line on the gate wiring side 56 also changes abruptly. To this end, the rush current also occurs at one or more portions having relatively low withstand voltages between the common line on the gate wiring side 56 and the gate wirings 13, among several hundred through more than a thousand of gate wirings 13 which exist near the common line on the gate wiring side 56. Therefore, electrostatic damage may occur in many portions. The above-mentioned disadvantages also occur with respect to the signal lines and the common line on the signal line side.
Considering the above-mentioned problems, the present invention has been made. It is a main object of the present invention to provide a thin film transistor array in which discharge between gate wirings and a common line on the gate wiring side and between signal lines and a common line on the signal line side caused by electrification, abnormal discharge and the like can be decreased.
It is another object of the present invention to provide a thin film transistor array in which occurrence of a rush current during a manufacturing process thereof can be suppressed.
It is still another object of the present invention to provide a thin film transistor array in which occurrence of electrostatic damage can be suppressed.
It is still another object of the present invention to provide a thin film transistor array in which damage of wirings and insulating films and occurrence of inferior characteristic of TFTs for display caused by electrification or abnormal discharge during a manufacturing process can be decreased.
According to an aspect of the present invention, there is provided a
According to another aspect of the present invention, there is provided a